A Novel High Speed Chinese Abacus Multiplier
نویسندگان
چکیده
Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm technology. The power consumption of the abacus multiplier is about 51% less than that of Braun array multiplier for 0.18μm technology.
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High Speed Multiplier Based on the Algorithm of Chinese Abacus
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